1. Field of the Invention
The present invention relates to a switching control circuit of synchronous rectification type.
2. Description of the Background Art
A main object of synchronous rectification is to reduce power loss produced on a discharge path when discharging an inductive load, by a parasitic diode and the like inside a semiconductor substrate.
When performing synchronous rectification, dead time needs to be provided in order to prevent the occurrence of short-circuit current due to a simultaneous turn-on of an output transistor for supplying load current and an output transistor for attracting load current.
A conventional technique related to such switching control circuit of synchronous rectification type is disclosed in “Transistor Technology, July 1998”, Vol. 35, No. 406 published by CQ Publishing Co., Ltd. on Jul. 1, 1998, Chapters 1-3.
An optimum value of dead time needs to be determined with various considerations as it depends on load current, load inductance or slew rate of output voltage. Various methods for determining dead time are known; however, an excessively short dead time will increase the risk that short-circuit current is produced, while an excessively long dead time will cause problems as will be described below.
Consider the case of driving an inductive load such as a coil or a motor using a CMOS transistor made up of a P-channel MOS transistor and an N-channel MOS transistor. In this case, even in a synchronous rectification type circuit, a parasitic bipolar transistor may disadvantageously be activated when an output potential (that is, a drain potential of the P-channel MOS transistor and N-channel MOS transistor) becomes not less than a power supply potential or not more than a GND potential during the dead time under the influence of inductive current in an inductance or a regenerative current in the motor.
In the case of the common source mode in which a bulk node as well as a P-channel MOS transistor and an N-channel MOS transistor are connected to the source, a parasitic vertical PNP bipolar transistor made up of a P+-type drain, an N-type bulk and a P−-type substrate is operated when a drain potential of the P-channel MOS transistor rises sufficiently above a source potential. As a result, a large amount of current flown out of an inductive load leaks into the substrate as collector current of the vertical PNP bipolar transistor, which cannot be used again. This not only reduces energy efficiency at the time of load driving, but also becomes a factor of unnecessary heat generation in an integrated circuit and a factor of an operation of a parasitic thyristor (a so-called latch-up) triggered by a substrate potential raised by the collector current of the vertical PNP bipolar transistor.
Further, when the drain potential of the N-channel MOS transistor falls sufficiently below the source potential, a parasitic NPN bipolar transistor made up of an N+-type drain, an P-type bulk and a N-type well adjacent to the bulk is operated. As a result, the P-type bulk attracts electric charge from the N-type well, which may not only reduce energy efficiency and cause unnecessary heat generation as described above, but may also cause malfunction of a circuit near the N-channel MOS transistor.
Accordingly, the dead time needs to be reduced to a minimum, particularly when driving a CMOS transistor by synchronous rectification.